The present invention generally relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having bonding pads arranged in a peripheral portion of a semiconductor chip, and peripheral circuits arranged in the vicinity of bonding pads. More particularly, the present invention relates to an improvement in the arrangement of bonding pads and chip peripheral areas used for forming a peripheral circuit such as an input buffer circuit, an output buffer circuit, or a bi-directional buffer circuit connected to bonding pads.
Conventionally, a plurality of pairs of bonding pads and peripheral circuits are arranged in a peripheral portion of a semiconductor chip. That is, one bonding pad is associated with one peripheral circuit. The above-mentioned arrangement of bonding pads and peripheral circuits creates easy layout design (repetition of one layout pattern) and a large degree of freedom to use bonding pads and related peripheral circuits.
Referring to FIG. 1, there is illustrated a conventional semiconductor integrated circuit device, which includes a semiconductor chip 10, an internal logic circuit area 12, and a chip peripheral area 14. The internal logic circuit area 12 includes a plurality of basic cells arrayed in matrix form, for example. In the chip peripheral area 14 surrounding the internal logic circuit area 12, there are arranged bonding pads 16, and peripheral circuits each having a P-channel transistor area 16a and an N-channel transistor area 16b used for forming a peripheral circuit (or an input/output cell). As is illustrated, one peripheral circuit made up of the transistor areas 16a and 16b is provided for each of the bonding pads 16.
FIG. 2A is an enlarged view of the bonding pad 16 and the P-channel and N-channel transistor areas 16a and 16b illustrated in FIG. 1. The P-channel and N-channel transistor areas 16a and 16b are located on both sides of the bonding pad 16 along an end of the semiconductor chip 10. The P-channel transistor area 16a and N-channel transistor area 16b are connected to the bonding pad 16 by connecting members 20a and 20b, respectively. A power supply line 18 is arranged in the vicinity of the P-channel and N-channel transistor areas 16a and 16b and the bonding pad 16 along the end of the semiconductor chip 10.
Turning now to FIG. 1, there are also a bonding pad 22 and a peripheral circuit area 24. FIG. 2B is an enlarged view of those parts. Referring to FIG. 2B, there are arranged the bonding pad 22, the peripheral circuit area 24 made up of N-channel and P-channel transistor areas 24b and 24a, and the power supply line 18 in this order from the end of the semiconductor chip 10. The P-channel and N-channel transistor areas 24a and 24b and the bonding pads 22 are mutually connected by connecting lines 26, as shown in FIG. 2B. One peripheral circuit is formed by the P-channel and N-channel transistor areas 24a and 24b.
Generally, the size of an output transistor used for forming an output buffer circuit must be large in order to obtain a high driveability for an external load. Even in an input buffer circuit, there is a need for a transistor having a large driveability. For example, a large number of flip-flops is driven by an external clock signal. The above holds true for a bi-directional circuit (an input and output circuit). The larger the size of output transistors, the larger the peripheral circuit area of the semiconductor chip. In the arrangement of FIG. 2A, the number of bonding pads 16 decreases with an increase of each of the P-channel and N-channel transistor areas 16a and 16b. In the arrangement of FIG. 2B, the internal logic circuit area 12 (FIG. 1) reduces with an increase of each of the P-channel and N-channel transistor areas 24a and 24b. This is because the area of each of the P-channel and N-channel transistor areas 24a and 24b must be increased toward the internal logic circuit 12 in order to increase the driveability. It can be seen from the above that there is room for improvement in arrangement of bonding pads and chip peripheral areas.